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Agilent HDMP-0450 Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops
Data Sheet
Description The HDMP-0450 is a Quad Port Bypass Circuit (PBC) which provides a low-cost, low-power physical-layer solution for Fibre Channel Arbitrated Loop (FC-AL) disk array configurations. By using a PBC such as the HDMP-0450, hard disks may be pulled out or swapped while other disks in the array are available to the system. A PBC consists of multiple 2:1 multiplexers daisy chained together. Each port has two modes of operation: "disk in loop" and "disk bypassed." When the "disk in loop" mode is selected, the loop goes into and out of the disk drive at that port. For example, data goes from the HDMP-0450's TO_NODE[n] differential output pins to the Disk Drive Transceiver IC's (e.g., an HDMP-1636A) Rx differential input pins. Data from the Disk Drive Transceiver IC's Tx differential outputs goes to the HDMP-0450's FM_NODE[n] differential input
pins. Figure 2 shows connection diagrams for disk drive array applications. When the "disk bypassed" mode is selected, the disk drive is either absent or nonfunctional and the loop bypasses the hard disk. The "disk bypassed" mode is enabled by pulling the BYPASS[n]pin low. Leave BYPASS[n]floating to enable the "disk in loop" mode. HDMP-0450s may be cascaded with other members of the HDMP-04XX/HDMP-05XX family through the appropriate FM_NODE[n] and TO_NODE[n] pins to accommodate any number of hard disks (see Figure 3). The unused cells in the HDMP-0450 may be bypassed by using pulldown resistors on the BYPASS[n]- pins for these cells. An HDMP-0450 may also be configured as five 1:1 buffers, as two 2:1 multiplexers, or as two 1:2 buffers.
Features * Supports 1.0625 GBd Fibre Channel operation * Supports 1.25 GBd Gigabit Ethernet (GE) operation * Quad PBC in one package * Signal detect on FM_NODE[0] input * Equalizers on all inputs * High speed LVPECL I/O * Buffered Line Logic (BLL) outputs (no external bias resistors required) * 0.5 W typical power at VCC = 3.3 V * 44 Pin, 10 mm, low-cost plastic QFP package Applications * RAID, JBOD, BTS cabinets * Two 2:1 muxes * Two 1:2 buffers * 1 => N gigabit serial buffer * N => 1 gigabit serial mux
HDMP-0450
CAUTION: As with all semiconductor ICs, it is advised that normal static precautions be taken in the handling and assembly of this component to prevent damage and/or degradation which may be induced by electrostatic discharge (ESD).
FM_NODE[1]
FM_NODE[2]
FM_NODE[3]
FM_NODE[4]
TO_NODE[0]
BYPASS[2]-
BYPASS[3]-
BYPASS[4]-
FM_NODE[0]
TO_NODE[1]
TO_NODE[2]
TO_NODE[3]
TO_NODE[4]
BYPASS[1]-
BYPASS[0]-
SD
EQU BLL TTL BLL EQU TTL BLL EQU TTL BLL EQU TTL BLL EQU TTL
TTL
SD
1 0
1 0
1 0
1 0
1 0
Figure 1. Block diagram of HDMP-0450.
HDMP-0450 Block Diagram BLL OUTPUT All TO_NODE[n] high-speed differential outputs are driven by a Buffered Line Logic (BLL) circuit that has on-chip source termination, so no external bias resistors are required. The BLL outputs on the HDMP-0450 are of equal strength and can drive in lengthy FR-4 PCB trace. Unused outputs should not be left unconnected. Ideally, unused outputs should have their differential pins shorted together with a short PCB trace. If longer traces or transmission lines are connected to the output pins, the lines should be differentially terminated with an appropriate resistor. The value of the termination resistor should match the PCB trace differential impedance.
EQU INPUT All FM_NODE[n] high-speed differential inputs have an Equalization (EQU) buffer to offset the effects of skin loss and dispersion on PCBs. An external termination resistor is required across all high-speed inputs. The value of the termination resistor should match the PCB trace differential impedance. Alternatively, instead of a single resistor, two resistors in series, with an AC ground between them, can be connected differentially across the FM_NODE[n] inputs. The latter configuration attenuates high-frequency common mode noise. BYPASS[n]- INPUT The active low BYPASS[n]- inputs control the data flow through the HDMP-0450. All BYPASS pins are LVTTL and contain internal pullup circuitry. To bypass a port,
the appropriate BYPASS[n]- pin should be connected to GND through a 1 k resistor. Otherwise, the BYPASS[n]-inputs should be left to float, as the internal pull-up circuitry will force them high. SD OUTPUT The Signal Detect (SD) block detects if the incoming data on FM_NODE[0] is valid by examining the differential amplitude of that input. The incoming data is considered valid, and SD is driven high, as long as the amplitude is greater than 400 mV (differential peak-topeak). SD is driven low as long as the amplitude of the input signal is less than 100 mV (differential peak-to-peak). When the amplitude of the input signal is between 100-400 mV (differential peak-to-peak), the SD output is undefined.
2
3
TO_NODE[1]
BLL
TO_NODE[1]
BLL
1
FM_NODE[1]
SERDES
EQU
1
HARD DISK A
BYPASS[1]-
SERDES
HARD DISK A
0
TTL
1
FM_NODE[1]
EQU
TO_NODE[2]
BLL
BYPASS[1]-
0
1
TTL
2
SERDES
FM_NODE[2] BYPASS[2]-
EQU
HARD DISK B
0
TTL
1
BLL
TO_NODE[3]
TO_NODE[2]
BLL
3
SERDES
FM_NODE[3]
2
EQU
HARD DISK C
SERDES
EQU
BYPASS[3]-
FM_NODE[2]
HARD DISK B
0
TTL
1
TO_NODE[4]
BYPASS[2]-
0
1
BLL
TTL
4
SERDES
FM_NODE[4] BYPASS[4]-
EQU
HARD DISK D
0
TTL
1
Figure 3. Connection diagram for multiple HDMP-0450s.
TO_NODE[3]
BLL
TO_NODE[0]
BLL
Figure 2. Connection diagram for Disk Array applications.
3
0
FM_NODE[0] = FM_LOOP
EQU
FM_NODE[3]
EQU
HARD DISK C
SERDES
BYPASS[0]- = HIGH (FLOAT)
0
TTL
1
BYPASS[3]-
0
1
TTL
TO_NODE[1] = TO_LOOP
BLL
1
FM_NODE[1] BYPASS[1]- = HIGH (FLOAT)
EQU
TO_NODE[4]
BLL
0
TTL
1
4
TO_NODE[2]
FM_NODE[4]
EQU
BLL
SERDES
HARD DISK D
2
SERDES
FM_NODE[2] BYPASS[2]-
EQU
HARD DISK E
BYPASS[4]-
0
1
0
TTL
1
TTL
TO_NODE[3]
BLL
3
SERDES
FM_NODE[3] BYPASS[3]-
TO_NODE[0] = TO_LOOP
BLL
EQU
HARD DISK F
0
TTL
1
0
FM_NODE[0] = FM_LOOP
EQU
TO_NODE[4]
BLL
4
SERDES
FM_NODE[4] BYPASS[4]-
EQU
BYPASS[0]- = HIGH (FLOAT)
0
1
HARD DISK G
TTL
0
TTL
1
TO_NODE[0]
BLL
SERDES
HARD DISK H
0
FM_NODE[0]
EQU
BYPASS[0]
0
TTL
1
I/O Type Definitions I/O Type I-LVTTL O-LVTTL HS_OUT HS_IN C S Definition LVTTL Input LVTTL Output High Speed Output. LVPECL Compatible High Speed Input External Circuit Note Power Supply or Ground
Pin Definitions Pin Name TO_NODE[0]+ TO_NODE[0]- TO_NODE[1]+ TO_NODE[1]- TO_NODE[2]+ TO_NODE[2]- TO_NODE[3]+ TO_NODE[3]- TO_NODE[4]+ TO_NODE[4]- FM_NODE[0]+ FM_NODE[0]- FM_NODE[1]+ FM_NODE[1]- FM_NODE[2]+ FM_NODE[2]- FM_NODE[3]+ FM_NODE[3]- FM_NODE[4]+ FM_NODE[4]- BYPASS[0]- BYPASS[1]- BYPASS[2]- BYPASS[3]- BYPASS[4]- SD Pin 24 25 07 06 44 43 38 37 31 30 10 09 04 03 41 40 35 34 28 27 14 15 16 17 18 20 Pin Type Pin Description HS_OUT Serial Data Outputs: High-speed outputs to a hard disk drive or to a cable.
HS_IN
Serial Data Inputs: High-speed inputs from a hard disk drive or from a cable.
I-LVTTL
Bypass Inputs: For "disk bypassed" mode, connect BYPASS[n]- to GND through a 1 k resistor. For "disk in loop" mode, float HIGH.
O-LVTTL
Signal Detect: Indicates acceptable signal amplitude on the FM_NODE[0] inputs. If (FM_NODE[0]+ - FM_NODE[0]-) >= 400 mV peak-to-peak, SD = 1 If 400 mV > (FM_NODE[0]+ - FM_NODE[0]-) > 100 mV, SD = undefined If 100 mV >= (FM_NODE[0]+ - FM_NODE[0]-), SD = 0
4
Pin Definitions, continued GND 01 08 11 12 13 19 22 23 33 39 26 05 42 36 29 02 21 32 S Ground: Normally 0 volts. See Figure 9 for Recommended Power Supply Filtering.
VCCHS[0] VCCHS[1] VCCHS[2] VCCHS[3] VCCHS[4] VCC
S S S S S S
High Speed Supply: Normally 3.3 volts. Used only for high-speed outputs (TO_NODE[n]). See Figure 9 for Recommended Power Supply Filtering.
Logic Power Supply: Normally 3.3 volts. Used for internal logic. See Figure 9 for Recommended Power Supply Filtering.
Absolute Maximum Ratings TA = 25C, except as specified. Operation in excess of any of these conditions may result in permanent damage to this device. Continuous operation at these minimum or maximum ratings is not recommended. Symbol VCC VIN,LVTTL VIN,HS_IN IO,LVTTL Tstg Tj Parameter Supply Voltage LVTTL Input Voltage HS_IN Input Voltage (Differential) LVTTL Output Sink/Source Current Storage Temperature Junction Temperature Units V V mV mA C C -65 0 Min. -0.5 -0.5 200 Max. 4.0 VCC + 0.5 [1] 2000 13 +150 +125
Note: 1. Must remain less than or equal to absolute maximum VCC voltage of 4.0 V.
DC Electrical Specifications VCC = 3.15 V to 3.45 V Symbol VIH,LVTTL VIL,LVTTL VOH,LVTTL VOL,LVTTL IIH,LVTTL IIL,LVTTL ICC 5 Parameter LVTTL Input High Voltage Range LVTTL Input Low Voltage Range LVTTL Output High Voltage Range, IOH = -400 A LVTTL Output Low Voltage Level, IOL = 1 mA Input High Current (Magnitude), VIN = 2.4 V, VCC = 3.45 V Input Low Current (Magnitude), VIN = 0.4 V, VCC = 3.45 V Total Supply Current, TA = 25C Units V V V V A A mA 150 2.2 0 Min. 2.0 0.8 VCC 0.6 40 -600 185 Typ. Max.
AC Electrical Specifications VCC = 3.15 V to 3.45 V Symbol TLOOP_LAT TCELL_LAT tr,LVTTLin tf,LVTTLin tr,LVTTout tf,LVTTout trs,HS_OUT tfs,HS_OUT trd,HS_OUT tfd,HS_OUT VIP,HS_IN VOP,HS_OUT Parameter Total Loop Latency from FM_NODE[0] to TO_NODE[0] Per Cell Latency from FM_NODE[4] to TO_NODE[0] Input LVTTL Rise Time Requirement, 0.8 V to 2.0 V Input LVTTL Fall Time Requirement, 2.0 V to 0.8 V Output TTL Rise Time, 0.8 V to 2.0 V, 10 pF Load Output TTL Fall Time, 2.0 V to 0.8 V, 10 pF Load HS_OUT Single-Ended Rise Time, 20%-80% HS_OUT Single-Ended Fall Time, 20%-80% HS_OUT Differential Rise Time, 20%-80% HS_OUT Differential Fall Time, 20%-80% HS_IN Required Peak-to-Peak Differential Input Voltage HS_OUT Peak-to-Peak Differential Output Voltage (Z0 = 75 , Figure 6) Units ns ns ns ns ns ns ps ps ps ps mV mV 200 1100 Min. Typ. 2.0 0.8 2.0 2.0 1.7 1.7 200 200 200 200 1200 1400 3.3 2.4 300 300 300 300 2000 2000 Max.
Guaranteed Operating Rates VCC = 3.15 V to 3.45 V FC Serial Clock Rate (MBd) Min. Max. 1,040 1,080 GE Serial Clock Rate (MBd) Min. Max. 1,240 1,260
Figure 4. Eye diagram of TO_NODE[1] high speed differential output (50 termination). Note: Measurement taken with a 2^7-1 PRBS input to FM_NODE[1].
6
Simplified I/O Cells
O_LVTTL
VCC
I_LVTTL
VCC
VCC
VBB 1.4 V
GND GND ESD PROTECTION ESD PROTECTION GND
Figure 5. O-LVTTL and I-LVTTL simplified circuit schematic.
HS_OUT
75 VCCHS VCC VCC
HS_IN
+ - VCC
+ -
TO_NODE[n]+
Z0 = 75
0.01 F
FM_NODE[n]+
2*Z0 = 150 TO_NODE[n]- Z0 = 75 GND ESD
PROTECTION
0.01 F
FM_NODE[n]- GND ESD
PROTECTION
GND
GND
NOTE: FM_NODE[n] INPUTS SHOULD NEVER BE CONNECTED TO GROUND AS PERMANENT DAMAGE TO THE DEVICE MAY RESULT.
Figure 6. HS_OUT and HS_IN simplified circuit schematic.
7
Package Information Power Dissipation and Thermal Resistance VCC = 3.15 V to 3.45 V Symbol PD jc[1] Parameter Power Dissipation Thermal Resistance, Junction to Case Units mW C/W Typ. 500 7 Max. 640
Note: 1. Based on independent package testing by Agilent. ja for this device is 57C/W. ja is measured on a standard 3x3" FR4 PCB in a still air environment. To determine the actual junction temperature in a given application, use the following equation: Tj = Tc + (jc x PD), where Tc is the case temperature measured on the top center of the package and PD is the power being dissipated.
Item Package Material Lead Finish Material Lead Finish Thickness Lead Skew Lead Coplanarity (Seating Plane)
Details Plastic 85% Tin, 15% Lead 200-800 micro-inches 0.33 mm max. 0.10 mm max.
Mechanical Dimensions
PIN #1 ID
1 2 3 4 5 6 7 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
28 27 26 8 9 25 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22
TOP VIEW
E1
E
D1 D
A2 c A A1 SEATING PLANE b e L 0.25 GUAGE PLANE
ALL DIMENSIONS ARE IN MILLIMETERS PART NUMBER E1/D1 HDMP-0450 TOLERANCE 10.00 E/D 13.20 b 0.35 e 0.80 L 0.88 c 0.23 A2 2.00 A1 0.25 A 2.45 MAX.
0.10 0.20 0.05 BASIC + 0.15/ MAX. + 0.10/ 0.25 - 0.10 - 0.05
Figure 7. HDMP-0450 package drawing.
8
Pin Diagram and Recommended Supply Filtering
FM_NODE[2]+ FM_NODE[3]+ FM_NODE[2]- FM_NODE[3]- TO_NODE[2]+ TO_NODE[3]+ TO_NODE[2]- TO_NODE[3]-
VCCHS[2]
44 43 42 41 40 39 38 37 36 35 34 GND VCC FM_NODE [1]- FM_NODE [1]+ VCCHS[1] TO_NODE [1]- TO_NODE [1]+ GND FM_NODE [0]- FM_NODE [0]+ GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 33 32 31 GND VCC TO_NODE[4]+ TO_NODE[4]- VCCHS[4] FM_NODE[4]+ FM_NODE[4]- VCCHS[0] TO_NODE[0]- TO_NODE[0]+ GND
VCCHS[3]
GND
Agilent HDMP-0450
nnnn-nnn Rz.zz S YYWW
30 29 28 27 26 25 24 23
BYPASS[0]-
BYPASS[1]-
BYPASS[2]-
BYPASS[3]-
BYPASS[4]-
nnnn-nnn = WAFER LOT - BUILD NUMBER Rz.zz = DIE REVISION S = SUPPLIER CODE YYWW = DATE CODE (YY = YEAR, WW = WORK WEEK) COUNTRY = COUNTRY OF MANUFACTURE (ON BACK SIDE)
GND
GND
GND
VCC
SD
Figure 8. HDMP-0450 package layout and marking, top view.
VCC
44 43 42 41 40 39 38 37 36 35 34 GND VCC 1 2 3 4 VCC 5 6 7 GND 8 9 10 GND 11 12 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 VCC GND VCC 10 F
HDMP-0450
GND
VCC
GND 28 27 26 25 24 23
VCC
GND
GND
GND
GND
GND
CAPACITORS = 0.1 F (EXCEPT WHERE NOTED).
Figure 9. Recommended power supply filtering.
9
VCC
www.agilent.com/semiconductors
For product information and a complete list of distributors, please go to our web site. For technical assistance call: Americas/Canada: +1 (800) 235-0312 or (408) 654-8675 Europe: +49 (0) 6441 92460 China: 10800 650 0017 Hong Kong: (+65) 6271 2451 India, Australia, New Zealand: (+65) 6271 2394 Japan: (+81 3) 3335-8152(Domestic/International), or 0120-61-1280(Domestic Only) Korea: (+65) 6271 2194 Malaysia, Singapore: (+65) 6271 2054 Taiwan: (+65) 6271 2654 Data subject to change. Copyright (c) 2002 Agilent Technologies, Inc. August 26, 2002 5988-7490EN

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